Digital signal processing (DSP) algorithms for a radio receiver are designed based on a set of presumptions about the signal statistics of a received signal. Most DSP algorithms presume a zero mean signal behavior, i.e., that the signal being processed has a zero DC bias. By assuming zero mean signal behavior, the DSP algorithm complexity can be kept simple, which in turn will keep the hardware implementation of that algorithm simple. As a result, receiver circuits will generally be designed such that they will have a zero DC bias.
However, although the receiver circuit may be designed to avoid a DC bias, such bias voltages can nevertheless arise from circuit mismatches, clock leakages, and other non-ideal aspects of a circuit. These DC bias elements can then serve to reduce overall radio performance by violating the presumptions in the receiver's DSP algorithms.
Thus it is generally desirable to both avoid DC biases and to provide methods to correct them when they inevitably appear. It would therefore be desirable to provide a receiver circuit that can minimize the effect of DC biases in its operation.